Test Architecture Plan, Boundry SCAN Design, Test insertion and ATPG

Logic SCAN is a requirement for the digital sections of ICs. IEEE 1149.1 JTAG or boundry scan is required for all ICs.
Click on the specification prompts on the right side of the flow diagram for the test specification outlines at each stage.
The design stage prompts on the left highlight tool setup, scripts, and engineering tasks required to complete the step.

Design Engineering

DFT Lead

&

Test Architect

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SCAN and JTAG
Overview

SCAN Standards Organization

JTAG 1149.1 Working Group

JTAG Defined (Wikipedia)

Database Layout and Timing Function Verification Engineering for Test Silicon Engineering Circuit Verification Circuit Verification Test and Manufacturing Circuit Design Circuit DFM Models and Timing Models and Timing Models and Timing Design Engineering

Tool Tips

SCAN & JTAG Tool Review

Test Tool Screen Shots

Tool Configuration

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JTAG & SCAN Supertap Conroller

Pro Test Development Environment

Test Engineering Design Manual

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