Resources and Solutions for Your SOC Design
From A Design Team With Over 160 Tapeouts of Experience In
Verilog RTL Design, IP, and Design Verification
Including Front End Design and Backend Layout Acceleration With
Physical Design & Manufacturing Test Experts
Focused on Manufacturing Quality, TCO, TTM, and Yield Managment
Design Stage Resource Locator
Circuit Level Design Resources
Tool Navigator
Vware Cores (Commercial IP)
DTware (SSI Team Cores)
Technology Libraries
- Gates and Clocks Generators
- I/Os and ESD Cells
- Process Monitor
IP Navigator
