The Brief, Our engineers average 20 years of IC design experience helping our clients in the areas of:

  • 1) Digital Architecture and logic design, RTL to gate level design, and verification
  • 2) Test architecture design, test insertion, and test program development
  • 3) Physical design and IC layout including IC to package engineering
  • 4) Integrating gates, memories, I/Os, clock structures, analog blocks, and IP into SOC ICs

The Detail, See below:

Design TaskObjectivePreferred Method
Specification Development Documented Specification Design to Specification
Verilog Module Design Design RTL modules for assigned blocks Editor + Modelsim/VCS
Test Bench Development Test functions and monitor test points VCS, Modelsim
Functional Verification Simulation and Waveform Analysis VCS, Modelsim
Coverage Analysis Test bench simulaiton coverage of 98%+ RTL code VCS, Modelsim
Timing Analysis Confirm design can meet timing requirements DC, Primetime, and VCS
Design TaskObjectivePreferred Method
Test Specification Development Clearly defined dft_test_spec.doc Text editor & block diagrams
Test Architecture Design
  • Test all functions
  • High fault coverage
  • Low tester time
  • BISR for large rams
  • At speed where needed
  • In house engineering
  • Block diagrams
  • .tcl and perl scripts
Boundry SCAN Design 1149.1 compliance and BSDL BSD Architect
Hierarchical SCAN Design Hierachical edt (compressor), hardmac, and top level Tessent
Memory BIST and BISR Design Test covergage & yeild improvement Logicvision
Logic BIST At Speed Test Logic Vision
ATPG High coverage with fewest vectors Tessent
Fault Coverage Analysis Fault grading to verify high test coverage Tessent and SSI scripts
Formal Verification Logic equivelance check after test insertion LEC
Design TaskObjectivePreferred Method
Datapath and Floorplan Design Performance and routability SOCEncounter
Congestion Analysis Routability with high layer utilization SOCEncounter
I/O placement P&G, SSO, ESD, mechanical rules SOCEncounter
I/O to Package Signal Engineering Pass signal integrity/spice analysis In-house
Power grid design IR drop, design power domains Voltage Strom
Metal layer/stack design Low layer count, increase utilization SOCEncounter
Timing closure Pass WC, BC, TC PrimeTime
Design for Manufacuring (DFM) Metal fill, GA backfill, wire spread SI Vendor Tools
LVS and DRCs Logic and Design rule checks Calibre
Design TaskObjectivePreferred Method
Specification Development Documented Specification Design to Specification
Feasibility Study Circuit and silicon requirements Layout and spice
Review Available Analog IP Verify avaialble circuit or new design Check IP specs and/or partner
Development plan Shuttle vs direct integration Reduce risk to minimum
ApplicationFunctions
Image Processor
  • 10 bit pixel processor
  • Edge detection algorithm for digital cameras
  • Programmable image scaler
Transport encoder LDPC core
Packet Processor 40G SFI layer one and 2 controller
Storage Controller
  • SCSI target protocol controller
  • Read Channel Encoding and Error Correction
I/O Controller Design USB Protocol design
DSP Functions
  • Analog Impairment removal module (100G enet)
  • Tomlinson-Harashima Precoder (THP)
  • Adaptive filter Echo-Next equalizer (512 taps)
  • Single Cycle Multiply/Accumulate (MAC, CMAC)
  • Compact carry-save building block
Memory Design
  • Asynchronous memories (Register file based)
  • CAM memory architecture design
Clock Design Data synchronizer for crossing clock domains