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Lead IC Test Expert With Comprehensive DFT Experience

  • A recognized leader in defining and developing the latest IC test methodologies
  • Proficient in all DFT design flows and design specific test methodology development
  • Formal verification expert for pre-test insertion to post, logic equivelency verification
  • Static and statistical timing analysis expert for timing verification after insertion
  • Experienced in fault coverage analysis for predictable device test coverage
  • Perl and Tcl script progamming expert for design automation

Test Architecture Specification, Design, and Implementation

  • Hierarchical Design For Test (DFT) methodology and design flow expert
  • Domain aware DFT synthesis set up and execution
  • Domain fencing for DC and ASST capture
  • Expert in all major fault tests: SCAN, JTAG, M & L BIST, BISR, I/O parametric test
  • Expert in process tests: TDF, IDDQ, Process Monitor Test, and Analog I/O test
  • On Chip Clock control insertion (OCC) for at speed test

Industry Test Standards Supported

  • Joint Test Action Group (JTAG): IEEE 1149.1, IEEE 1149.6
  • Embedded Core Test: IEEE 1500
  • SCAN and Automatic Test Pattern Generation
  • ATPG coverage analysis and SCAN chain timing closure
  • SCAN chain reordering for routing optimization
  • SCAN vector compression for lowering tester time

Core Blocks Test and Repair: IP Cores, Memories, Logic

  • On Chip Clock Controll For At Speed and Transition Delay Fault Testing
  • At Speed Logic Test (lBIST)
  • Memory At Speed Test (mBIST)
  • Memory Built In Repair (mBISR)

Standard and Special I/O Test Design and Development

  • TTL, SSTL, HSTL, LVDS, HSS, I/O test set up and program development
  • PLL VCO open loop tests and on chip clock control
  • I/O Parametric Tests and tristate tests, LoHi, HiLo, HiZ
  • Static IDD, and IDDq
  • Voltage control and measure tests for analog I/O

Analog Integration, Test, and Verification Expertice

  • Signal Integrity definition, analysis, modeling, and test
  • High Speed Serdes Integration
  • Spice simulation and analysis
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Portfolio of Projects Engineered

  • Lead Engineer for tape outs to IBM, LSI, TI, & ST for designs in CU11/130nm, CU08/90nm, CU65/65nm and CU45/45nm CMOS technologies. Static timing analysis performed with Einstimer, signal integrity analysis, GPM hspice simulation. Differential clock design, layout, and spice analysis.

  • HSS (High Speed Serdes) core integration with IBM's HSSCDR program to analyze and predict signal quality in the high speed data channels

  • Hierarchical timing closure and differential clock analysis for 20 million gate CU65 ASIC for high performance switching processor for metro network.

  • Timing analysis and signal integrity engineering for a 2 CU11/130nm 400MHz+ for Telecom ASIC applied to mobile enterprise solutions and Telecom.

  • DFT architecture and design for 7 million gate DSL chip in CU65/65nm CMOS technology using the Synopsys flow. Responsible for JTAG (bsd compiler), memory bist (Virage SMS) insertion, adaptive scan with multiple compressors (Synopsys dftmax & tetramax), and at speed testing with OCC (on-chip clock control).

Design Tools and Technical Skills

  • DFT and ATPG: Dftadvisor, Fastscan, Bsdarchitect, DFTmax, Tetramax, Virage SMS System, and Logicvision

  • Syntheis: Designcompiler and RTL compiler

  • Signal integrity: hspice, and IBM's HSSCDR

  • ASIC/VLSI logic design: Verilog RTL coding, logic simulation; Synopsys VCS simulation, Design synthesis, Conformal formal verification, Mentor Modelsim simulation, SignalScan, Debussy

  • STA Tools: Primetime SI and IBM Einstimer

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