Design Tool:
Source File:
Control File:
Control Script Example:
Scan insertion: input files: module_dfta.dof ( dftadvisor do file) module.v (pre scan netlist) run_dfta_module (run script for dfta) output files: module_scan.v (scan inserted input) module.subchain ( subchain defination) module_dfta.log (dftadvisor log file) dftadvisor ./vortex_top_postdft.v \ -verilog -lib ../../../lib/all.mlib \ -nogui -top linkport \ -log linkport_dfta.log \ -sen \ -rep \ -dof linkport_dfta.dof add sub chains linkport chain1 SI_1 SO_1 1134 mux_scan SCAN_EN -subclock sclk add sub chains linkport chain2 SI_2 SO_2 1134 mux_scan SCAN_EN -subclock BIST_CLK_LV_1 add sub chains linkport chain3 SI_3 SO_3 1134 mux_scan SCAN_EN -subclock rbc_clk add sub chains linkport chain4 SI_4 SO_4 1134 mux_scan SCAN_EN -subclock sclk add sub chains linkport chain5 SI_5 SO_5 1134 mux_scan SCAN_EN -subclock sclk add sub chains linkport chain6 SI_6 SO_6 1134 mux_scan SCAN_EN -subclock sclk add sub chains linkport chain7 SI_7 SO_7 1134 mux_scan SCAN_EN -subclock sclk add sub chains linkport chain8 SI_8 SO_8 1134 mux_scan SCAN_EN -subclock sclk add sub chains linkport chain9 SI_9 SO_9 1134 mux_scan SCAN_EN -subclock sclk Core level scan insertion input files: core.v module_scan.v core.subchain (subchain definition) scan_order.in (scan order file and chain balancing) output files: core_scan.v core_dfta.log MEMBIST Flow: MBIST Controller generation input files: memory.lvlib (memory library model) controller.membist (configration file) run_controller (run script for controller generation) output files: MEMBIST Controller Insertion Cont'd controller.gtool_info controller.vb (RTL for controller) collar.vb (RTL for collar) controller.syn (synthesis script for controller) collar.syn (synthesis script for controller) controller.log tb_controller.v (stand alone testbench for the controller) Controllers and collars assembly input files: core.v all controller.v, collar.v, and files from the membistg directories core.designa ( config file for designAssemble) output files: core.v_designa ( core file with membist inserted), designa.log membistg rxb_mbist.membist \ -clockPeriod 7.2 \ -library G13UP2304X34R332C.lvlib \ -DaisyChain On \ -failurelimit 10000 \ -parallelStaticRetention On \ -compStat on \ -outDir rxb_cntrl etv vortex_top \ -configFile vortex_top.etvConfig \ -outDir etv_out \ -packageDir ./bsdl_dir \ -reportSimProgress On \ -verilog On \ -vif vif_dir \ -wgl On