Design Tool:

Source File:

Control File:

Control Script Example:

Scan Design Rule Check:
	1.	Clock control.
	2.	Asynchronous set/reset control.
	3.	Scan ordering (negative edge flop, testramax rule S29).
	4.	Tris-state driver control.
	5.	All asynchronous loop should be avoided
	6.	DO NOT USE CROSS-COUPLED NAND/NOR.
	7.	Bi-directional output pad control.
	8.	Tri-state outputs of embedded memory must be disabled in scan test mode.
	9.	Tri-state and bid-directional outputs of embedded core/IP must be disabled during scan.
	10.	Testability improvement of shadow logic of memories and embedded core by test point insertions (i.e inputs of blackbox module are not observable and outputs are not controllable).
	11.	Lockup latch insertion if needed.
	12.	Test mode STA (no hold time violations from Q to SI pin)
Confirm STA(Static Timing Analysis) in scan test mode.
Confirm whether the STA tool have case analysis feature to set the circuit to scan test mode.  PrimeTime has case analysis feature. 
Confirm scan test mode setting in STA scripts and STA results.
	13.	Test clock control ( one-hot during scan capture or dynamic clock grouping).
	14.	Review the use of clock as data.
	
Signoff 
	Vector Generation / Formatting
	Formal Verification 
	Final DFT Review 
	ASIC Vendor specific signoff