TAP ?BSR Insertion:
input files
- pad.library (I/O pad library)
- chip.pinorder (pin order file)
- top_module.chiptesta (configuration file)
- run_designa (run scripts)
output files:
- top_module.v_chiptesta (ouput top level netlist)
- top_module.bsdl (BSDL file for this design)
- JTAP.vb (RTL for TAP controller)
- BSR.vb (RTL for boundary scan registers)
- JTAP.synopsys (synthesis scripts)
- BSR.synthesis (synthesis scripts)
- chiptesta.log ( log file for chiptesta run)
SSI software/scr: generate chiptesta and pinorder.
chiptesta xyz8440 ./vortex_top.v \
- -r vortex_top \
- -pinOrderList xyx8440.pinorder \
- -extension scan:vb:v \
- -v /projects/xyz/library/tsmc13/verilog/tsmc13io_9.v \
- -y /projects/xyz/library/tsmc13/sc/v3/verilog/generic/generic \
- -y /projects/xyz/library/tsmc13/io/v9/verilog/sdf-v2.1/generic \
- -padLibrary ./pad.library \
- -outdir JTAG_OUT \
- -clockPeriod 50 \
- -userConfiguration xyz8440.chiptesta
Verification tool:
- LV testbench
Input files:
- top_module.bsdl
- run_tapbistv
Output files:
- TB_TAP.v (testbench)
- TB_TAP.wgl ( wgl file for tester)
- tapbistv.log (log for tapbistv)
- tapbistv vortex_top \
- -bsdlFile JTAG_OUT/xyz8440.bsdl \
- -activeControlCells 8 \
- -clampTest On \
- -clockPeriod 20 \
- -flatten on \