Design Tool:

Source File:

Control File:

Control Script Example:

Static Timing Analysis (test mode)
Test mode sta scripts
1. JTAG/BSCAN
2. Scan shift
3. Scan capture
4. Memory BIST

JTAG and BSCAN scripts
create_clock -name DFT_CLOCK  -period 50.00 [list tck  ]
create_clock -name DFT_CLOCK2 -waveform { 25 50 } -period 50.00 [get_pins tap_i/clockdr_bsr  ]

scan shift sta:
Create_clock -name SCAN_CLK1  -period 40.00 -waveform [0 10 30 ] [get_ports  MFI_A1 ]
create_clock -name SCAN_CLK2  -period 40.00 -waveform [0 10 30 ] [get_ports  MFI_A2 ]
set_case_analysis 1 U_dft_test/SCAN_EN_toCore
report_timing -to [get_pins */TI] -hier

scan capture sta;
create_clock -name SCAN_CLK1  -period 40.00 -waveform [0 10 30 ] [get_ports  MFI_A1 ]
create_clock -name SCAN_CLK2  -period 40.00 -waveform [0 10 30 ] [get_ports  MFI_A2 ]
set_false_path -from SCAN_CLK1 -to SCAN_CLK2
set_false_path -from SCAN_CLK2 -to SCAN_CLK1
set_case_analysis 0 U_dft_test/SCAN_EN_toCore
report_timing -to [get_pins */D] -hier

membist sta:
create_clock -name BIST_CLK  -period 10.00 -waveform [0 2.5 7.5 ] [get_ports  MFI_A1 ]
set_propagate_clock BIST_CLK
set_case_analysis 1 LVISION_JTAP_INST/bistEN0