Preliminary Analysis:
- Understand the scope of the design
- Review clocking scheme
- Review test mode logic
- Development test plan
- Prepare for test document
- Trace all flip flops in the prelimary netlist
- Use primetime to report all clocks, set and reset
- Review all internally generated clocks/set/reset
- Add bypass muxes if necessary
- netlist split (perl script)
input: customer netlist
- perl script to cut the netlist
ouput: top_module.v core.v
- software/scr: xtract_module
Initial Design Analysis
- Clock Domains Analysis
- Scanability Analysis
- Membist architecture (memory grouping)
- TAG configuration
- Test Integration Plan
Checklist for High Fault Coverage
- Minimize number of undetectable fault because of ATPG constraints.
- Minimize number of undetectable fault because of gated clocks.
- Avoid undetectable faults because of improper test logic insertion (e.g disabled OR or by-pass mux).
- Minimize number of gated clock or internally generated clocks.
- Minimize number of internally generated set/reset.
- If possible do not use tri-state drivers.
- Minimize number of latches.
- Do not use clock signal as data.
- Added test point before scan synthesis if possible
Implementation Phase
- DFT - Scan, ATPG, JTAG, MBist, IDDQ, etc
- Formal verification
- Fault Coverage Analysis & Enhancements
- Integration of all test modes & IP tests
- Design Review