Preliminary Analysis:

  • Understand the scope of the design
  • Review clocking scheme
  • Review test mode logic
  • Development test plan
  • Prepare for test document
  • Trace all flip flops in the prelimary netlist
  • Use primetime to report all clocks, set and reset
  • Review all internally generated clocks/set/reset
  • Add bypass muxes if necessary
  • netlist split (perl script)

input: customer netlist

  • perl script to cut the netlist

ouput: top_module.v core.v

  • software/scr: xtract_module

Initial Design Analysis

  • Clock Domains Analysis
  • Scanability Analysis
  • Membist architecture (memory grouping)
  • TAG configuration
  • Test Integration Plan

Checklist for High Fault Coverage

  1. Minimize number of undetectable fault because of ATPG constraints.
  2. Minimize number of undetectable fault because of gated clocks.
  3. Avoid undetectable faults because of improper test logic insertion (e.g disabled OR or by-pass mux).
  4. Minimize number of gated clock or internally generated clocks.
  5. Minimize number of internally generated set/reset.
  6. If possible do not use tri-state drivers.
  7. Minimize number of latches.
  8. Do not use clock signal as data.
  9. Added test point before scan synthesis if possible

Implementation Phase

  1. DFT - Scan, ATPG, JTAG, MBist, IDDQ, etc
  2. Formal verification
  3. Fault Coverage Analysis & Enhancements
  4. Integration of all test modes & IP tests
  5. Design Review

The above steps form the basis for a standard test development plan. If you found this useful send us a google like or more. If you need a test design team, that is one of our specialties.