Compiler directives to handle different versions of Verilog:

If your synthesis tool or simulator supports the different Verilog HDL revisions the tool will have switches for the version of verilog it is compiling. With each version of verilog, backward compatibility with the older versions is preserved as a default. It is recommended that you set up your simulator and synthesis compilers for the latest version of Verilog that the point tool supports to enable proper handeling of all modules regardless of theVerilog revision level used for to construct the modules in the design.

Each new version of verilog introduces new keywords. Using keywords of a newer version of Verilog with the compiler set to an older version will cause a warning or a compiler error.

In addition some compilers and simulators may not support all of the newest features and design constructs of the Verilog language. Check your verilog verision switch settings, log files, tool keyword support, and consult with your tool vendor if you are seeing compilation errors not related to design constructs.